Processor Array Design and Adaptive Computing
Research Contracts and Grants:
- Principal-Investigator (with Dr. Karen Tomko), "Application Accelerating Reconfigurable Computer," Air Force Research Lab/Dayton Graduate Institute; from April 2000 to April 2002.
- Principal-Investigator (with Dr. Guozhu Dong), "Query Optimizing Reconfigurable Computing System," Systran Federal Inc.; from April 2000 to January 2001.
- Principal-Investigator, "Dynamically Reconfigurable Computing," Ohio State Board of Regents; from July 1998 to June 2000.
- Principal Investigator (with Dr. Karen Tomko), "A Framework for Speculative Run-Time Reconfiguration," Defense Advanced Research Projects Agency; from September 1997 to May 2000.
- Principal Investigator (with Dr. Karen Tomko), "A Run-Time Reconfiguration System," Ohio State Research Challenge Grant; from June 1997 to May 1998.
- Co-Investigator (with Oscar Garcia as P.I. and others), "Information Technology Center Infrastructure," Ohio Board of Regents Fund for Equipment; from March 1996 to February 1999.
- Principal Investigator, "Research Initiation Award: Fault Tolerant Processor Array," National Science Foundation; from August 1989 to January 1992.
- Principal Investigator (with Dr. Raymond E. Siferd), "Engineering Research Equipment Grant: A VLSI Array Compiler System (VACS)for Array Design," National Science Foundation; from August1989 to January 1992.
- Principal Investigator, "Documentation for the Array Compiler VACS," Hughes Aircraft Company; from November 1989to December 1989.
- X. Liang, J.S.N. Jean, and K. Tomko, "Data Buffering and Allocation in Mapping Generalized Template Matching on Reconfigurable Systems," to appear in The Journal of Supercomputing, Special Issue on Engineering of Reconfigurable Hardware/Software Objects.
- J.S.N. Jean, X. Liang, B. Drozd, K. Tomko, and Y. Wang, "Automatic Target Recognition with Dynamic Reconfiguration," Journal of VLSI Signal Processing, Vol. 25, pp. 39--53, May 2000.
- J.S.N. Jean, K. Tomko, V. Yavagal, J. Shah, and R. Cook, "Dynamic Reconfiguration to Support Concurrent Applications," in IEEE Transactions on Computers, Special Issue on Configurable Computing, Vol. 48, No. 6, pp. 591--602, June 1999.
- J. Fernando and J.S.N. Jean, "Processor Array Design with FPGA Area Constraint," in IEEE Transactions on CAD of ICs and Systems, Vol. 18, No. 3, pp. 253--264, March 1999.
- J.S.N. Jean, X. Liang, and K. Tomko, "Data Buffering and Allocation in Mapping Generalized Template Matching on Reconfigurable Systems," in the Proc. of Parallel and Distributed Processing Techniques and Applications Conference, pp. 1111--1117, June 1999.
- J.S.N. Jean, K. Tomko, V. Yavagal, R. Cook, and J. Shah, "Dynamic Reconfiguration to Support Concurrent Applications," in the Proc. of IEEE Symposium on FPGAs for Custom Computing Machines, April 1998.
- Robert Cook, Jack Jean, Jer-Sen Chen, "Accelerating MPEG-2 Encoder Utilizing Reconfigurable Computing", CERC/VIUF/IEEE Computer Society Workshop on "21st Century Electronic Systems Design: Breakthroughs in Quality and Productivity", University of Dayton, December 1997.
- J. Fernando and J.S.N. Jean, "Interfacing FPGA/VLSI Processor Arrays," in Proc. IEEE International Conference on Application Specific Array Processors, pp. 230--237, July 1995.
- J. Spillane and J.S.N. Jean, "Mapping Nested Loops to Field Programmable Gate Array Based Systems," in Proc. IEEE National Aerospace and Electronics Conference, pp. 227--231, May 1995.
- J.S.N. Jean and S.Y. Kung, "Array Compiler Design for VLSI/WSI Systems," in TRANSFORMATIONAL APPROACHES to SYSTOLIC DESIGN, edited by G.M. Megson, Chapman & Hall, U.K., 1993.
- S.N. Jean, "Reconfigurable Processor Arrays with Two-Track Switches," in Proc. IEEE National Aerospace and Electronics Conference, pp. 434--440, May 1992.
- S.N. Jean and S.Y. Kung, "Fault-Tolerant RectangularArray Processors via Reconfiguration," in RECONFIGURABLE MASSIVELY PARALLEL COMPUTERS, PP. 223--249, edited by Hungwen Li, Prentice Hall, New Jersey, 1991.
- Joseph Fernando, "Mapping Algorithms to Processor Arrays," Ph.D. Dissertation, August 1997.
- Gerald Berry, "A Design Methodology for FPGA-Based Digital Filters," 1996
- Abd-Alrazzak Habra, "A Simulator for Fault Tolerant Array Processors," 1993
- Noshin Kagalwalla, "A Parallel Neural Network Architecturefor the Recognition of Handwritten Digits," 1993
- Hemang Mehta, "A Simulator for Real Time Fault Tolerancefor Mesh Interconnection Networks," 1992
Last Revised 7/27/2000